Synthesis of Diagnosable FET Networks

With the advent of field-effect transistor (FET) technology it has become practical and economical to employ complex functions as network primitives. This paper describes a synthesis procedure for diagnosable (all single and multiple faults can be detected) FET networks. A companion procedure for generating tests to detect all faults in the resulting network is also described. This methodology does not guarantee the minimality of the network, however, it is intuitively understandable and easy to apply. Index Terns-Fault diagnosis, FET network, irredundant function, network synthesis, single and multiple faults. INTRODUCTION T HE concept of carrying out a hardware design without a conscious effort to incorporate diagnostic capability into the unit is not only costly in terms of the results of undetectable faults that may arise, but may also be costly in terms cYf the time that is spent in deriving fault tests, which, in turn, may be incomplete. Therefore, it is suggested that diagnosis should be very much of a design issue. Up to quite recently, simple logic gates (OR, AND, NOR, and NAND) have been used to implement Boolean functions. With the advent of field-effect transistor (FET) technology it has become both practical and economical to employ more complex functions as network primitives. The manner in which functions are realized by FET devices is similar to contact networks seen in the early stages of switching theory. Ibaraki and Muroga [2] have developed an algorithm for designing switching networks using only gates that represent complex functions. The word "gate" in this context refers not to a single FET device but, rather, to the combination of devices that produce a given function; hence "gate" is closer to the word "module." This paper will consider the synthesis of diagnosable FET networks using a procedure that is an adaptation of the work of Ibaraki and Muroga. The networks that will be constructed, however, are done so with the aim of simplifying the diagnosis problem and not, necessarily, guaranteeing minimality. The design is intended to be coinpletely diagnosable, that is, all single and multiple faults can be detected. An easy and efficient procedure for generating a sufficient set of fault-detection tests for the network is also presented. Manuscript received March 13, 1972; revised November 9, 1972. This work was supported in part by the Joint Services Electronics Program under Contract DAAB-67-C-0199 and in part by the International Business Machines Corporation. Portions of this paper were presented as a Short Note at the 1971 Spring Joint Computer Conference in conjunction with Prof. G. Metze, Coordinated Science Laboratory, University of Illinois, Urbana-Champaign, Ill. The author was with the Coordinated Science Laboratory, University of Illinois, Urbana-Champaign, Ill. He is now with General Research Corporation, Santa Barbara, Calif. 93105. SYNTHESIS OF FET NETWORKS It has been shown [2] that a function F(x) is negative if there is no pair of comparable vectors Xi and Xi such that Xi > Xi, and, F(X1) = 1 and F(Xj) = 0. For example, the functiOn F(X1, X2, X3) represented by its truth table in Table I is not a negative function since (100) > (000), and, F(100) = 1 and F(OOO) = 0. The FET module shown in Fig. 1 will be used as the primitive for the networks to be synthesized. The function G(X) in the figure is formed by the contact-like network of FET's. The output function F(X) would be equal to G(X) and is formed by an auxiliary FET that is also used to create the proper loading capabilities for the module. Without loss of generality it will be assumed that the output function to be realized is given in the following form: F(X) = G(X) = PI (X) + P2(X) + * + Pn(X) (1) where G(X) is irredundant, and each Pi(X) is a product term. It is obvious that each product term Pi(X) in (1) can be divided into two factors: a positive product term Pi(X) and a negative product term Pi'(X). Either Pi(X) or P7 (X) can be equal to 1. For the function given by Table I, for example, the following representation can be made: F(X)=G(X)=x1x3 +x1x2 +x1x2x3 where P1 (X) =x1x3, P2 (X) = x 1 x2, and P3 (X) = X IX2X3. The first step in the synthesis procedure is to generate a function Li(X) for each Pi(X) such that we have the following. Rule 1: For each vector Xt such that Pl(Xt) = 1 set Li(Xt) = Pilet). Rule 2: If Li(Xk) = 0 then for all vectors Xt such that Xk > Xt, set Li(Xt) = 1. Rule 3: If Li(Xk) = O then for all vectors Xt such that Xt > Xk, set Li(Xt) = 0. Rules 2 and 3 are included so that Li(X) will be a negative function. The auxiliary function Li(X) for the product terms in the example are shown in Table I. Note that entries that could not be filled using Rule 1 are filled using Rules 2 and 3 wherever possible. DONT CARE entries emerge due to nonapplicability of the above rules. It is straightforward to demonstrate that replacing each Pi'(X) by its respective Li(X) function does not change G(X) (or F(X)). The second step in the procedure is to merge the Li(X) functions wherever possible using the DON'T CARE positions. In this manner one L1(X) function can fulfill the requirements (if possible) of several others. There are several well-known tabular methods for combining the above type of function (such as Quine-McCluskey [6] and so they will not be discussed here further. It should suffice to 513 IEEE TRANSACTIONS ON COMPUTERS, MAY 1973 TABLE I TRUTH TABLE AND FUNCTIONS FOR EXAMPLE XI X2 X3 I F(X) G(X) L1(X) L2(X) L3(X)1L2/3(X)